...turns your Motorola "MC micro" into a fully-fledged amateur radio transceiver.

Hardware and Software - The Juicy Details

The controllers (HD6303) used by Motorola in the MC micro series (and identical radios) were built in the 1980s and can therefore not compete with microcontrollers available today. Computing power is especially limited, the core clock is 2 MHz at best and most instructions take 3-4 cycles to complete. These and other limitations require otimized and creative programming (especially in speed critical parts). Due to assembly not being the most comprehensible programming language, this page is going to explain some of the essential parts of the firmware. Also the hardware interface (pin-out and connections, etc.) is described.

Model EVA5 (Command Board GLN7059B)

XTAL 7,9776 MHz
CPU / Core clock 1,9944 MHz
RAM (CPU intern) installed: 256 Byte
  accessible: 256 Byte
RAM (extern) installed: 8192 Byte
  accessible: 7680
ROM (extern) installed: 65536 Byte
  accessible: 57344 Byte

Memory Layout

Address Range Belegung
$0000 - $0027 Registers
$0028 - $003F not accessible*
$0040 - $013F internal Memory
$0140 - $01FF not accessible*
$0200 - $2000 external RAM
$2000 - $FFFF external ROM

* These addresses access external memory. However the address decoder (RAM/ROM switch) in the MC micro only permits access in the ranges $0200 - $1FFF (RAM) and $2000-$FFFF (ROM), therefore read access at external adresses below $0200 yields undefined data.

CPU I/O Port Pin Allocation

Port Pin Name Function
2.0 9 Signalling Decode Input from the RX Comparator (1-Bit "ADC")
2.1 10 Data Synchronous serial Bus (EEPROM, PLL, Shift Register) Data
2.2 11 Clock Synchronous serial Bus (EEPROM, PLL, Shift Register) Clock
2.3 12 SCI RX UART/RS232 Rx From Control Head
2.4 13 SCI TX UART/RS232 Tx To Control Head
2.5 14 T/R Shift VCO (RX/TX) Switch 0=Tx, 1=Rx
2.6 15 Alert Tone Towards Audio PA, 1-Bit-DAC for local audio
2.7 16 Shift Reg Latch Towards Shift Register Latch Input, Latest 8 bits from serial bus are latched in on positive edge
5.0 17 Emergency From rear Sub-D connector, Input 0 = 0 V on pin 9. FSK-Mod cuts this connection and rewires Sub-D pin 9.
5.1 18 Power Fail From 9.6 V Regulator, 1=Power Fail (Input voltage < 9,8 V)
5.2 19 SW B+ From rotary switch on control head, 1 = radio powered
5.3 20 Ext. Alarm Towards rear Sub-D connector, Open Collector output, 1 = Output 0 V, MC70 uses this to signal the squelch condition
5.4 21 HUB/PGM From rear Sub-D connector and Control Head/Microphone (Hub Switch), signals suspended microphone
5.5 22 Lock Detect 0 V = PLL locked
5.6 23 SQ Det From Carrier Squelch, 1 = Signal exceeds threshold
5.7 24 RSSI From RSSI Board / Squelch, 1 = Signal exceeds threshold
6.0 25 Key 3/4 Detect From Control Head, connected to Port 2.3/SCI RX
6.1 26 Key 1 From Control Head, connected to Port 2.4/SCI TX
6.2 27 Key 2 From Control Head, connected to Port 6.4/#Test
6.3 28 Syn Latch Towards PLL, rising edge latches data from serial bus into PLL register
6.4 29 Yel LED/#Test Output towards Control Head and Input from test pin (TEST)
6.5 30 Signalling Encode D/A MSB Tx audio signalling Bit 1
6.6 31 Signalling Encode D/A LSB Tx audio signalling Bit 0
6.7 32 PTT From Control Head, 1 = PTT active